Logic Design and Verification Using SystemVerilog (Revised)
A revised educational resource on logic design and verification using SystemVerilog. Written by Donald Thomas, it introduces the subject for readers studying digital logic, hardware description languages, and the practices used to develop and verify digital systems.
About This Book
Logic Design and Verification Using SystemVerilog (Revised) focuses on the study of logic design and verification through SystemVerilog.
It is intended as an educational resource for readers exploring digital logic and hardware description languages.
The revised edition presents its subject in a format suited to learning, reference, and continued study.
Written by Donald Thomas, this book may support students and practitioners seeking a foundation in SystemVerilog-based design and verification.
Reviews
No reviews yet. Be the first to review this book!